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Testing out my Papilio FPGA!

Recently, I got hold of a Papilio One (which you can think of as the Arduino of FPGAs).  The Papilio board has a Xilinx Spartan 3 on board, which is plenty enough to get started learning about FPGAs.  Here’s what the board looks like:

Now, it might look big above … but it’s not!  You can see the Spartan FPGA in the middle, the micro USB port in the bottom left and the three banks of I/O pins (two in the top left, one in the top right).

Now, the question is: what do you do with this thing? Well, that’s what I’ve been figuring out.  The first thing you need is the Xilinx IDE which you can download and use for free.  Then, you need to learn VHDL or Verilog. I went for VHDL and have been reading “Free Range VHDL” which has a freely available electronic version.  Then, I got hold of a bread board and some LEDs and connected it all up like this:

Here, we’ve got two LEDs connected to the output pins of the Papilio.  Then, I wrote a VHDL program which implements a two bit counter clocked by one of the inputs (i.e. so the counter increments whenever we see a rising edge on the input):

entity Counter is
Port (
 W1A : in  STD_LOGIC_VECTOR(15 downto 0);
 W1B : out  STD_LOGIC_VECTOR(15 downto 0);
 W2C : out  STD_LOGIC_VECTOR(15 downto 0);
 rx : in STD_LOGIC;
 tx : inout STD_LOGIC;
 clk : in STD_LOGIC
);
end Counter;

architecture Behavioral of Counter is
signal counter : STD_LOGIC_VECTOR(1 downto 0) := (others => '0');
begin
process(W1A(0))
begin
 if rising_edge(W1A(0)) then
  counter <= counter +1;
 end if;
end process;
 W2C(1 downto 0) <= counter;
 W2C(15 downto 2) <= "00000000000000";
 W1B <= "0000000000000000";
end Behavioral;

You can see here that pin 0 from the A bank of inputs (i.e. W1A) is being used to clock the counter. This is then written to the first 2 pins of the C bank (i.e. W2C), with all other output pins pulled to 0. Anyhow, you can see the whole in action here:


Anyway, that’s a bit of fun. But, the question is: why am I doing this? Well, the answer is that: I want to compile Whiley programs to run on an FPGA. Obviously, this is going to take a while to get going, but these are the first steps. The plan is use the Papilio to drive my tracked robot (which is currently controlled by an Arduino):

Anyhow, that’s what I’ve been working on today …

3 comments to Testing out my Papilio FPGA!

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